In situ characterization of CMOS post-process micromachining

We have developed and demonstrated a new methodology for in situ monitoring and characterization of CMOS post-process micromachining utilizing integrated circuits and micromachine test-structures. In our demonstration, the circuits provide automated readout of N-well resistors surrounding each of the 140 test pit structures at up to 14,000 samples per second per device during the post-process silicon etch and, thus, also provide etch progress and end point determination without extra analytical equipment. We use this technique to examine the effect of pit size, surrounding thin ®lm layers, and topology in a 2 mm CMOS process with a XeF2 post-process step, although the technique and results are of use to EDP, TMAH, and plasma post-processing. # 2001 Elsevier Science B.V. All rights reserved.